Analog-to-digital converters (ADC) play an important role in microcontroller based systems. Nowadays, there is a strong trend towards low power design of microcontroller based systems and since ADCs consume significant power during their operation, it becomes imperative to build low power ADCs.
An ADC according to the invention works with successive approximation, well known as one of the basic principles for analog-to-digital conversion. A typical ADC comprises a successive approximation register SAR, a digital-to-analog converter DAC, a comparator COMP and a sample and hold stage SHS. The basic functionality of an ADC using successive approximation will be explained with reference to FIG. 1.
During a first clock cycle that is triggered by the clock input CLK, an input voltage VIN that is sampled by the SHS is compared to a reference voltage VREF. If the result of the comparison indicates that VIN is greater than VREF, a respective bit decision relating to the most significant bit (MSB) is made. During a subsequent cycle, the next less significant bit (MSB−1) is determined. The conversion procedure carries on accordingly and the DAC output voltage converges successively to the analog input voltage VIN, while evaluating one bit during each clock cycle. When the conversion is completed, the status of the SAR is the digitized representation of VIN. This digital value is output by the ADC and the SHS samples the next analog input voltage VIN to be converted.
For precise analog-to-digital conversion, capacitive DACs are frequently used in ADCs. FIG. 2 shows a capacitive DAC stage comprising a plurality of capacitors C . . . C128. Each capacitor C . . . C128 is associated to one bit, i.e. C is associated to the least significant bit (LSB), C2 is associated to LSB+1, C4 is associated to LSB+2, etc. The exemplary digitization depth is 8-bit and accordingly, C128 is associated to the eight and most significant bit (MSB). The ratio between the capacities of capacitors C . . . C128 equals their bit indices. For example, the ratio between the capacitances C4 and C128 is equal to 4 to 128.
Before the first clock cycle of analog-to-digital conversion occurs, the SAR is initialized by a reset. This means that all capacitors C . . . C128 are set to a common potential defined as low. During the first clock cycle, the MSB is set to high, i.e. capacitor C128 is charged by setting it to a predetermined second potential. All other capacitors remain at low. The resulting voltage VCOMP is output by the capacitive ADC to the comparator COMP and depending on whether the analog input voltage VIN is greater or lower than VCOMP the MSB is left at high or set to low. During the next clock cycle MSB−1 is determined by charging C64 and performing the same test at the comparator COMP between the new value of VCOMP and VIN. Successively, VCOMP approaches VIN bit by bit as shown in FIG. 3.
The successive approximation register SAR is shown in more detail in FIG. 4. During each bit decision, the successive approximation register SAR stores the status of capacitors C . . . C128. The SAR comprises a sequencer having a plurality of flip-flops F . . . FN and a code register comprising a plurality of flip-flops R0 . . . RN. At the beginning of analog-to-digital conversion all flip-flops are set to low. During each clock cycle the state of one flip-flop of the code register is determined. The final state of the flip-flops is the digital code, i.e. the digital approximation of VIN and is finally output by the SAR of the ADC at the end of conversion.
An advantage of the successive approximation procedure according to the prior art is its simplicity and predictability. Within n+1 cycles, wherein n is the number of analog-to-digital conversion resolution bits, also known as a digitization depth (in the previous example n=8), the result is available to the remainder of the system.
However, the above described method of analog-to-digital conversion is power consuming. The main power consuming elements throughout the n+1 cycles are the comparator and the charging and discharging of the capacitor array. Most power reduction techniques known in the art focus on improvements in one or more of these elements.